Tutorial Speaker

Rajit Manohar

Computer Systems Lab at Yale, USA

Title: An ASIC Flow for Asynchronous Logic

Summary: The complexity of modern VLSI chips requires the use of design automation tools. Digital asynchronous circuits do not use clocks for their operation, and this violates the built-in assumption of synchrony in most electronic design automation (EDA) tools. We discuss the gaps in the EDA flow, and the new pieces of the flow that we have created that enable the automated design of complex asynchronous circuits.


Bio.: Rajit Manohar is the John C. Malone Professor of Electrical Engineering and Professor of Computer Science at Yale. He received his B.S. (1994), M.S. (1995), and Ph.D. (1998) from Caltech. He has been on the Yale faculty since 2017, where his group conducts research on the design, analysis, and implementation of self-timed systems. He is the recipient of ten best paper awards, nine teaching awards, and was named to MIT technology review's top 35 young innovators under 35 for contributions to low power microprocessor design. His work includes the design and implementation of a number of self-timed VLSI chips including the first high-performance asynchronous microprocessor, the first microprocessor for sensor networks, the first asynchronous dataflow FPGA, the first radiation hardened SRAM-based FPGA, and the first deterministic large-scale neuromorphic architecture. Prior to Yale, he was Professor of Electrical and Computer Engineering and a Stephen H. Weiss Presidential Fellow at Cornell. He founded the Computer Systems Lab at both Cornell and Yale. He has served as the Associate Dean for Research and Graduate studies at Cornell Engineering, the Associate Dean for Academic Affairs at Cornell Tech, and the Associate Dean for Research at Cornell Tech. He founded Achronix Semiconductor to commercialize high-performance asynchronous FPGAs.